1. Field of the Invention
The present invention concerns a digital phase detector and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL).
In general terms a PLL serves the purpose of synchronising a controllable oscillator, which generates an output signal with an output frequency, with an input clock signal with an input frequency, by means of feedback. For this purpose the PLL comprises a phase detector or phase comparator, at whose input the input clock signal and the PLL output signal are present. A signal representing the respective phasing between these two signals is mainly used to control the oscillator via an active or passive, digital or analog filter (“loop filter”).
2. Description of the Prior Art
The areas of application for PLL circuits are many and varied. For example PLLs can be used for clock signal recovery from digital signal sequences, or for FM demodulation. In communications standards such as “SONET” or “SDH” clock generation circuits are required to generate clock signals during the transmission and receipt of data. In a circuit of this kind a PLL circuit can generate, e.g. from an input clock signal inputted as a reference, one or a plurality of output clock signals for use in a communications system.
In accordance with prior art based on knowledge within the business organisation of the applicant an approach for the implementation of a digital phase detector consists in combining an analog phase detector with a downstream analog-digital converter. The phase resolution thus achievable is however severely limited by the linearity of the analog phase detector and also the resolution of the analog-digital converter. Therefore in accordance with another approach a digital phase detector has been implemented with a sampling circuit in which an input clock signal supplied to the phase detector is sampled by means of a higher frequency sampling clock signal, likewise supplied to the phase detector (“oversampling”). The phase resolution is then definitively determined by the sampling rate (frequency of the sampling clock signal), wherein, however, the maximum sampling frequency is limited in practice by the speed of the electronic components used in the sampling circuit.